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    • 专利摘要:
    A silicon oxide film is deposited on the substrate by first introducing a process gas into the chamber. Process gas is a gaseous source of silicon (such as silane), an oxygen gaseous source (such as SiF 4 ), a gaseous source of oxygen (such as nitrogen oxides), and a gaseous form of nitrogen (such as N 2 ). Contains the source. The plasma is formed from the process gas by applying an RF power component. Deposition is carried out at a rate of at least about 1.5 μm / min. The resulting FSG film is stable and has a low dielectric constant.
    公开号:KR19980081561A
    申请号:KR1019980014119
    申请日:1998-04-21
    公开日:1998-11-25
    发明作者:다이안 수기아르토；쥬디 휴앙；데이비드 쳉
    申请人:조셉제이.스위니；어플라이드머티어리얼스,인코포레이티드；
    IPC主号:
    专利说明:

    A process for depositing a high deposition rate halogen doped silicon oxide layer.
    The present invention relates to a method and apparatus for the deposition of a halogen doped dielectric layer during wafer processing, more particularly the formation of a high deposition rate halogen doped silicon oxide layer with low dielectric constant and high film stability.
    One of the initial steps in the manufacture of modern semiconductor devices is the formation of a thin film on a semiconductor substrate by a chemical reaction of gas. Such deposition process is called chemical vapor deposition, or CVD. A typical thermal CVD process is to supply a reaction gas to the surface of a substrate to produce a film desired by a thermally induced chemical reaction. At high temperatures during the thermal CVD process, damage to the device structure with the metal layer can occur.
    Other CVD methods for depositing a layer over a metal layer at relatively low temperatures include plasma enhanced CVD (PECVD) techniques. Plasma CVD technology generates plasma by applying radio frequency (RF) energy to a reaction region near the substrate surface to promote excitation and dissociation. The high reactivity of the species in the plasma reduces the energy needed for the chemical reaction to occur, lowering the temperature required for such CVD processes. The relatively low temperature of the PECVD process makes this process ideal for forming insulating layers or other insulating layers on deposited metal layers.
    The size of semiconductor devices has been dramatically reduced in size since such devices were first introduced decades ago. Since then, integrated circuits have generally followed a two-year / half-size rule (sometimes called Moore's Law), which means that the number of components on a chip doubles every two years. Today's wafer fabrication plant mechanically produces 0.5 µm and even 0.35 µm integrated circuits, and future plants will soon produce much smaller devices.
    As devices become smaller and more dense, problems that have not been considered important in the industry have come to the fore. With the advent of multilayer metal technology in which metals with three, four or more layers are formed over semiconductors, one purpose of semiconductor manufacturers has been to lower the dielectric constant of an insulating layer deposited between metal layers. Such layers are often referred to as intermetal dielectric (IMD) layers. Low dielectric constant films in the IMD layer are particularly desirable to reduce the RC time delay of interconnect metallization, to prevent cross talk between different levels of metallization, and to reduce the power consumption of the device.
    Many approaches have been proposed to achieve low permittivity. One of the more promising solutions is to mix fluorine with other halogen elements such as chlorine and bromine into the silicon oxide layer. Fluoride, the preferred halogen impurity for silicon oxide, is thought to lower the dielectric constant of silicon oxide because fluorine is an electronegative atom that reduces the polarization of the entire SiOF network. Fluorine-doped silicon oxide films are also called silicon fluoride glass (FSG) films.
    FSG membranes can be deposited using fluorine sources such as CF 4 , C 2 F 6 and NF 3 . One particular method of depositing an FSG film is plasma from a process gas containing precursors of silicon tetrafluoride (SiF 4 ), silane (SiH 4 ), and oxygen (O 2 ) as a source of fluorine. To form. SiF 4 is thought to be a particularly effective source of fluorine for FSG membranes, which, compared to other fluorine sources, has a higher percentage of four fluorine atoms bonded to silicon atoms in the gas molecule at a given flow rate. This is because fluorine is supplied to the deposition chamber. In addition, SiF 4 has more fluorine bonded to silicon to be used in the plasma reaction than other fluorine sources. The use of SiF 4 as a source of fluorine for FSG films is described in US patent application Ser. No. 08 / 538,696, filed Oct. 2, 1995, entitled Use of SiF 4 to deposit F-doped films with better stability. And US patent application Ser. No. 08 / 616,707, entitled Methods and Devices for Improving Film Stability of Halogen Doped Silicon Oxides, filed March 15, 1996. The applications of 08 / 538,696 and 08 / 616,707 have been assigned to Applied Materials Inc., the assignee of the present invention.
    Therefore, manufacturers want to include fluorine in various dielectric layers and in particular intermetallic dielectric layers. One problem encountered in the deposition of the FSG layer is membrane stability. Loosely bonded fluorine atoms in the lattice structure of the FSG film make the film tend to absorb moisture. The absorbed moisture increases the dielectric constant of the film and can cause another problem if the film is placed in a thermal process such as an anneal process.
    Absorbed water molecules and loosely bound fluorine atoms can escape from the oxide layer through the metal layer or other subsequently deposited layer due to the high temperature in the thermal process. This release of molecules and atoms is called outgassing. Such leakage is measured by detecting fluorine, hydrofluoric acid (HF) or water (H 2 O) leaving the membrane when the membrane is heated to a certain temperature. It is desirable that at least the FSG film has little or no leakage at a temperature up to the highest temperature used during the substrate process after deposition (eg, up to 450 ° C at any moment).
    In general, the permittivity of an FSG film is related to the amount of fluorine contained in the film. Increasing the fluorine content of the membrane generally decreases the dielectric constant of the membrane. By the way, FSG membranes with higher fluorine content (e.g., fluorine than 7 or 8 atomic percent) are more likely to have water absorption or leakage problems than membranes with lower fluorine content (e.g., less than 7 or 8 atomic percent fluorine). Easier to have Therefore, it is necessary to develop an oxide film having a low dielectric constant so as not to lag behind the new technology.
    In addition, a method of increasing the stability of halogen doped oxide films, especially FSG films with high fluorine content, thereby reducing water absorption and leakage in the films is also desirable.
    Another concern for manufacturers is the throughput of the process. High throughput requires high deposition rates in the process. Therefore, in order to improve the deposition efficiency, the membrane must have a high deposition rate in addition to the stability.
    It is an object of the present invention to provide a halogen doped layer with low dielectric constant and improved stability even at high halogen doping levels. The present invention also provides methods and apparatus for forming such layers with high deposition rates.
    1A and 1B are vertical, cross-sectional views of one embodiment of a chemical vapor deposition (CVD) apparatus in accordance with the present invention.
    1C and 1D are exploded views, perspective views of a portion of the CVD chamber shown in FIG. 1A.
    1E illustrates a simplified diagram of a system monitor and CVD system 10 in a multichamber system that may have one or more chambers.
    1F illustrates an example block diagram of a hierarchical control structure of a computer program 70 and system control software, in accordance with certain embodiments.
    2A-2B illustrate a flow chart illustrating process steps in the formation of an insulating layer in accordance with a preferred embodiment of the method of the present invention.
    FIG. 2C is a chart illustrating the effects on the doping effect, deposition rate, and film quality of various variables in a process. FIG.
    3A-3B are simplified cross-sectional views of an insulating film deposited as a cap layer in accordance with the present invention.
    3C-3D are simplified cross-sectional views of an insulating film deposited in accordance with the present invention in a damascene process.
    4A-4L illustrate different test results showing the effect of increasing concentration of fluorine on the stability of the insulating film of the present invention.
    Explanation of symbols on the main parts of the drawings
    11: branch pipe 12: pedestal
    15a: chamber wall 15b: chamber lid assembly
    16: slot hole 17: filling space
    42: blocking plate 44: RF power supply
    50a: CRT monitor 50b: light pen
    Membrane stability is improved by injecting a nitrogen source gas and a halogen source gas together with a silicon and oxygen source into the deposition chamber. Next, a plasma is formed from the gas to deposit the halogen doped layer onto the substrate placed in the deposition chamber. It is recognized that the injection of a nitrogen source improves the stability of the layer by reducing the amount of loosely bonded or unbound fluorine in the layer.
    FSG membranes are deposited according to a preferred embodiment of the method of the present invention. In this example, the nitrogen source gas is N 2 and the halogen source gas is SiF 4 . The oxygen source is N 2 O and the silicon source is SiF 4 . The ratio of N 2 to SiF 4 is between about 3 and 20, and the ratio of N 2 to SiH 4 is between about 3 and 10. In addition, the ratio of N 2 to N 2 O is between about 0.5 to 4. Deposited FSG membranes according to this embodiment may contain up to at least 16 atomic percent fluorine as measured using secondary mass ion spectroscopy (SIMS). In addition, the membrane substantially shows no leakage of fluorine or HF from the layer even when heated to temperatures up to at least 475 ° C. and 500 ° C., respectively. In a more preferred embodiment of the method of the present invention, at the completion of the deposit step, the flow of SiF 4 is stopped for several seconds before the flow of other process gases is stopped. Adopting this sequence reduces the loosely bound fluorine in the membrane and results in deposition of the FSG membrane containing at least 16 atomic percent of fluorine and leakage of fluorine, HF, H 2 O from the layer even when heated to at least 700 ° C. This is substantially gone.
    These and other embodiments of the present invention are described in more detail in the following text and the accompanying drawings, along with several advantages and features.
    I. Introduction
    The present invention provides a high deposition rate insulating layer with low dielectric constant and improved film stability. The present invention also provides a method and apparatus for forming such an insulating layer. Improved stability and low permittivity characteristics are obtained by introducing a nitrogen source such as N 2 into the process gas, for example.
    As discussed above, FSG films with high fluorine content generally have a lower dielectric constant than similar films with lower fluorine content. SiF 4 is a particularly effective fluorine source because it has four fluorine atoms bonded to one silicon atom and supplies a higher percentage of fluorine to the deposition chamber at a given flow rate than other fluorine sources. However, excessive unbound fluorine in the plasma adversely affects the stability of the film. This is because excess unbound fluorine generally reacts to form SiF 2 bonds in the film, and SiF 2 bonds are likely to absorb water and form HF and silanol (SiOH). This is undesirable because HF may escape from the membrane and the membrane may subsequently peel off or break. In addition, the SiOH remaining in the film degrades the film's dielectric constant over time when the film is exposed to stresses of humidity and temperature.
    Therefore, the method of removing unbound fluorine from the plasma to prevent the formation of SiF 2 in the film is important to ensure film stability. Nitrogen gas reacts with unbonded or loosely bonded fluorine atoms during deposition to form NF 2 or NF 3 , which are recognized as volatile gases that can be easily removed from the deposition chamber during or after deposition. have. Therefore, such unbonded or loosely bonded fluorine atoms are prevented from participating in the various reactions that form the growing film. This results in the next smaller number of loosely bonded fluorine atoms included in the FSG layer. Since fewer loosely bonded fluorine atoms are present in the FSG layer, leakage in the next process step is also reduced, thereby ensuring membrane stability.
    In addition, SiF 4 is a particularly suitable fluorine source for high deposition rate processes. In general, an increase in the fluorine content of CF 4 , C 2 F 6 , and NF 3 FSG membranes is associated with more corrosion of the membrane while the membrane is deposited. In contrast, an increase in the fluorine content of the SiF 4 FSG film improves the dielectric constant of the film, while only a minimal additional corrosion of the film is affected by the increased fluorine content. Therefore, using SiF 4 as a fluorine source further improves deposition efficiency.
    In a preferred embodiment, the process gas comprises fluorine supplied from SiF 4 , silicon supplied from SiH 4 , oxygen supplied from N 2 O, and nitrogen supplied from N 2 . The membrane is deposited at a rate of about 1.5-1.8 μm / min. The dielectric constant of the film is about 3.3-3.5 as measured by the CV curve at 1 MHz in the metal insulator semiconductor (MIS) structure. The film contains about 7 percent SiF (measured by Fourier transform infrared (FTIR) spectroscopy of the highest ratio of SiF bonds to SiF + SiO bonds) and may comprise at least 16 atomic percent fluorine as measured by SIMS. As a result, when deposited according to a preferred embodiment of the process of the invention, the membrane is substantially free of fluorine, HF, or H 2 O leakage from the layer even when heated to at least 700 ° C.
    II. Example CVD System
    A suitable CVD apparatus capable of carrying out the method of the present invention is shown in Figures 1A and 1B, which includes a vacuum or process chamber comprising a chamber wall 15a and a chamber lid assembly 15b. Is a vertical, cross-sectional view of a CVD system 10 having a. Chamber wall 15a and chamber lid assembly 15b are shown in exploded, perspective view in FIGS. 1C and 1D.
    The CVD system 10 includes a gas distribution branch 11 for dispersing the process gas to a substrate (not shown) over a heated pedestal 12 centered in the process chamber. During the process, the substrate (eg, semiconductor wafer) is located on the flat (or slightly convex) surface 12a of the pedestal 12. The pedestal can be controlled to move from the lower mounting / removing position (shown in FIG. 1A) to the upper process position (shown with a hatch 14 in FIG. 1A and also shown in FIG. 1B) very close to the branch pipe 11. Can be. The centerboard (not shown) includes a sensor for providing information at the location of the wafer.
    The deposition and carrier gas are introduced into the chamber 15 through the perforated holes 13b (FIG. 1D) of a conventional flat, circular gas distribution or faceplate 13a. More specifically, the deposition process gas through the inlet branch 11 (indicated by the arrow 40 in FIG. 1B), through a conventional perforated barrier plate 42, the hole of the gas distribution face plate 13a. It flows into the chamber via 13b.
    Before reaching the branch pipe, the deposition and carrier gas are sent from the gas source 7 to the mixing system 9 via the gas feed line 8 (FIG. 1B), mixed and then sent to the branch pipe 11. In general, each process gas supply line includes (i) several safety shut-off valves (not shown) that can automatically or manually shut off the flow of process gas into the chamber, and (ii) the flow of gas through the supply line. A mass flow controller (not shown) to measure. Typically, when toxic gas is used in the process, several safety shut-off valves will be located for each gas supply line.
    The deposition process performed in the CVD system 10 may be a thermal process or a plasma-enhanced process. In the plasma enrichment process, the RF power supply 44 applies power between the gas distribution faceplate 13a and the pedestal to stimulate the process gas mixture to form a plasma in the cylindrical region between the faceplate 13a and the pedestal. (This region is referred to herein as the reaction region). The components of the plasma react to deposit the desired film on the surface of the semiconductor wafer supported on the pedestal 12. RF power supply 44 may be a mixed frequency RF power supply that typically supplies high RF frequency (RF1) of 13.56 MHz and low RF frequency (RF2) of 360 KHz. Alternatively, the power supply may only supply high frequency RF power of 13.56 MHz or low frequency RF power of 360 KHz. RF power supply 44 is used to facilitate the decomposition of reactive species introduced into vacuum chamber 15. In the thermal process, no RF power supply 44 is used, and the process gas mixture reacts thermally to deposit the desired film on the surface of the semiconductor wafer supported on the pedestal 12, the pedestal being resistively heated. ) Supply thermal energy for reaction.
    During the plasma enhanced deposition process, the plasma heats the entire process chamber 10 including the chamber wall 15a surrounding the exhaust gas passage 23 and the shutoff valve 24. When not in the plasma state or during the thermal deposition process, hot liquid is circulated through the wall 15a of the process chamber to maintain the chamber at a high temperature. Fluids used to heat the chamber wall 15a include typical fluids, such as water-based ethylene glycol or oil-based heat transfer fluids. This heating reduces or eliminates the condensation of undesirable reactants and contaminates the process gas volatiles and other contaminants that may contaminate the process if condensed on the walls of the cold vacuum passages or returned to the process chamber while there is no gas flow. Removal of material is promoted.
    The remainder of the gas mixture not deposited in the bed, including the reactants, is withdrawn from the chamber by a vacuum pump (not shown). In detail, the gas is discharged into an annular discharge plenum through an annular, slotted hole 16 surrounding the reaction zone. The annular slot 16 and the fill space 17 are defined as the gap between the top of the cylindrical sidewall 15a (including the top dielectric layer of the wall) and the bottom of the circular chamber lid 20. The 360 ° circular symmetry and uniformity of the slot hole 16 and the fill space 17 are important for obtaining a uniform flow of process gas over the wafer to deposit a uniform film on the wafer.
    The gas passes from the discharge fill space 17, down the side extension portion 21 of the discharge fill space 17, past the viewing port and through the gas passage 23 extending downward. It passes through the vacuum shutoff valve 24 (integrated in the lower chamber wall 15a) and through the foreline (not shown) to the outlet 25 which is connected to an external vacuum pump (not shown).
    The wafer support platter (preferably aluminum, ceramic, or a mixture thereof) of the pedestal 12 is resistively heated using a built-in single loop built-in heater element formed to make two complete turns in the form of parallel concentric circles. . The outside of the heater element extends adjacent the edge of the support disc, and the inside of the heater element extends over a path of concentric circles having a smaller radius. The wiring to the heater element passes through the axis of the pedestal 12.
    Typically, any or all chamber interiors, gas inlet branch faceplates, and various other reactor hardware are made of a material such as aluminum, anodized aluminum, or ceramic. An example of such a CVD apparatus is described in US Pat. No. 5,558,717 to Zhao et al. Entitled CVD Processing Chamber. Patent 5,558,717 was assigned to Applied Materials, Inc., the assignee of the present invention, the entirety of which is incorporated herein by reference.
    The lift mechanism and motor 32 (FIG. 1A) move the heater as the wafer moves into or out of the chamber through an insertion / removal hole 26 on the side of the chamber 10 by a robot blade (not shown). Raise and lower the pedestal assembly 12 and its wafer lift pins 12b. The motor 32 raises and lowers the pedestal between the processing position 14 and the lower wafer loading position. The motor, the valve or flow controller connected to the supply line 8, the gas delivery system, the throttle valve, the RF power supply 44, and the chamber and substrate heating system are all controlled by the system controller 34 (FIG. 1B). 36), only a part of which is shown. The controller 34 relies on feedback from the light sensor to measure the position of the movable mechanical assembly, such as the throttle valve and the pedestal, moved by the appropriate motor under the control of the controller 34.
    In a preferred embodiment, the system controller includes a hard disk drive (memory 38), a floppy disk drive and a processor 37. The processor includes a single board computer (SBC), analog and digital input / output boards, interface boards and step motor controller boards. Various parts of the CVD system 10 follow the Versa Modular European (VME) specification, which defines the dimensions and types of boards, card cages, and connectors. The VME specification also defines the bus structure as a bus structure with a 16-bit data bus and a 24-bit address bus.
    System controller 34 controls all operations of the CVD apparatus. The system controller executes system control software, which is a computer program stored on a computer-readable medium, such as memory 38. The memory 38 is preferably a hard disk drive, but may be other types of memory. The computer program includes a combination of instructions that indicate timing, gas mixture, chamber pressure, chamber temperature, RF power level, pedestal position, and other variables of the individual process. For example, computer programs stored on other memory devices, including floppy disks or other suitable drives, may also be used to operate the controller 34. The interface between the user and the controller 34 is through a CRT monitor 50a and a light pen 50b, which is shown in FIG. 1E. 1E is a simplified diagram of a system monitor and CVD system 10 in a substrate processing system that may include one or more chambers. In a preferred embodiment, two monitors are used, one attached to the clean room wall for the operator and the other behind the wall for the service technician. The monitors 50a can display the same information at the same time, but only one light pen 50b is allowed. An optical sensor at the end of the light pen 50b senses the light emitted from the CRT display. To select a particular screen or function, the operator touches a designated area of the display screen and presses a button of pen 50b. The touched area changes color that is highlighted, or a new menu or screen is displayed to confirm communication between the light pen and the display screen. Other devices, such as a keyboard, mouse or other pointing or communicating device, may also be used in place of or in addition to the light pen 50b to allow the user to communicate with the controller 34.
    The process of depositing the film may be performed using a computer program product executed by the controller 34. Computer program code may be written in any conventional programming language readable by a computer: for example, 68000 assembly language, C, C ++, Pascal, Fortran, and the like. Appropriate program code is input into a single file or a plurality of files by a conventional text editor, and stored and stored in a computer usable medium such as a computer memory system. If the entered code text is written in a high level language, the code is compiled and the resulting compiler code is then linked with the object code of the precompiled Windows TM library routines. To execute the linked and compiled object code, the system user calls the object code to cause the computer system to load the code into memory. The CPU then reads and executes the code to perform the tasks identified in the program.
    1F is an exemplary block diagram of a hierarchical control structure of system control software, computer program 70, according to certain embodiments. In response to the menu or screen displayed on the CRT monitor, the user enters the process set number and process chamber number into the process selector subroutine 73 using the light pen interface. A process set is a predetermined set of process variables needed to carry out a particular process and is identified by a predetermined set number. The process selector subroutine 73 identifies the set of process variables desired (i) and process parameters (ii) desired to operate the process chamber to perform the desired process. Process variables for performing a particular process relate to process conditions such as, for example, process gas conditions, flow rate, temperature, pressure, plasma conditions such as RF power level and low frequency RF frequency, cooling gas pressure, and chamber wall temperature. There is this. These variables are provided to the user in the form of prescriptions and entered using the light pen / CRT monitor interface.
    Signals for monitoring the process are provided by the analog and digital input boards of the system controller, and signals for controlling the process are output to the analog and digital output boards of the CVD system 10.
    Process sequencer subroutine 75 includes program code that receives the process chamber and set of process variables identified in process selector subroutine 73 and program code that controls the operation of the various process chambers. Since multiple users may enter process set numbers and process chamber numbers, and one user may enter multiple process set numbers and process chamber numbers, sequencer subroutine 75 schedules the selected processes in the desired order. Works.
    Preferably, the orderer subroutine 75 comprises (i) monitoring the operation of the process chamber to determine if the chamber is being used, (ii) measuring what processes are being performed in the chamber being used, And (iii) program code for executing the desired process based on the availability of the process chamber and the type of process to be performed. As with polling, conventional methods of monitoring the process chamber can be used. When scheduling which processes are to be executed, the orderer subroutine 75 may determine the desired process conditions for the selected process, or the age of the request entered by each particular user, or by the system programmer to determine the scheduling order. Consider the current conditions of the process chamber in use compared to any other related elements to be included.
    Once the orderer subroutine 75 determines which process chamber and process set combination is to be executed next, the orderer subroutine 75 determines the process chamber according to the process set determined by the orderer subroutine 75. In 15), the chamber manager subroutines 77a-c that control multiple processing tasks are given specific process set variables to initiate execution of the process set. For example, chamber manager subroutine 77a includes program code for controlling sputtering and CVD process operation in process chamber 15. Chamber manager subroutine 77 also controls the execution of various chamber component subroutines that control the action of the chamber components needed to perform the selected process set.
    Examples of chamber component subroutines include substrate positioning subroutine 80, process gas control subroutine 83, pressure control subroutine 85, heater control subroutine 87, and plasma control subroutine 90. There is this. Those skilled in the art will readily appreciate that other chamber control subroutines may be included depending on which process is performed in process chamber 15. In operation, chamber manager subroutine 77a selectively schedules or invokes process component subroutines depending on the particular set of processes performed. Manager subroutine 77a schedules the process component subroutines as if sequencer subroutine 75 schedules which process chamber 15 and process set to run next. Typically, the chamber manager subroutine 77a monitors various chamber components, determining which components need to be actuated based on process variables for the process set to be performed, and monitoring stages. And causing the execution of the chamber component subroutine in response to the determining step.
    The action of certain chamber component subroutines is now described with respect to FIG. 1F. The substrate positioning subroutine 80 mounts the substrate on the pedestal 12 and optionally raises the substrate to the desired height of the chamber 15 to control the gap between the substrate and the gas distribution branch 11. Program code for controlling the chamber components used. When the substrate is mounted into the process chamber 15, the pedestal 12 is lowered to receive the substrate and thereafter, during the CVD process, the pedestal 12 is maintained to maintain the original distance or distance from the gas distribution branch. 12) is raised to the desired height of the chamber. In operation, the substrate positioning subroutine 80 controls the movement of the pedestal 12 in response to process set variables related to the support height delivered from the chamber manager subroutine 77a.
    The process gas control subroutine 83 has program code for controlling process gas mixing and flow rate. The process gas control subroutine 83 controls the open / close position of the safety shutoff valve and also ramps up / down the mass flow controller to obtain the desired gas flow rate. The process gas control subroutine 83 is invoked by the chamber manager subroutine as all chamber component subroutines do, and the process gas control subroutine 83 is also associated with the desired gas flow rate from the chamber manager subroutine. Take a variable. Typically, the process gas control subroutine 83 opens the gas supply line and repeatedly (i) reads the required mass flow controller, and (ii) compares the desired flow rate with the read value received from the chamber manager subroutine 77a. And (iii) adjusting the flow rate of the gas feed line as needed. Moreover, process gas control subroutine 83 includes monitoring the gas flow rate against unsafe rates and actuating a safety shutoff valve when an unsafe condition is detected.
    In some processes, an inert gas such as helium or argon is introduced into the chamber 15 before the reaction process gas is introduced to stabilize the pressure in the chamber. For this process, the process gas control subroutine 83 is programmed to include introducing an inert gas into the chamber 15 for the time necessary to stabilize the pressure in the chamber, and the steps described above are then performed. In addition, when the process gas is evaporated from a liquid precursor, such as, for example, tetraethylorthosilane (TEOS), the process gas control subroutine 83 is helium-like through the liquid precursor in the bubbler assembly. Bubbling the delivery gas, or introducing a carrier gas such as helium or nitrogen into the liquid injection system. When a bubbler is used in this type of process, the process gas control subroutine 83 adjusts the flow of delivery gas, pressure in the bubbler, and bubbler temperature to obtain the desired process gas flow rate. As discussed above, the desired process gas flow rate is passed to the process gas control subroutine 83 as a process variable. In addition, the process gas control subroutine 83 accesses a stored table containing the necessary values for a given process gas flow rate, thereby providing the required delivery gas flow rate, bubbler pressure for the desired process gas flow rate. And obtaining the bubbler temperature. Once the required values are obtained, the delivery gas flow rate, bubbler pressure and bubbler temperature are monitored and compared with the required values and adjusted accordingly.
    The pressure control subroutine 85 includes program code for controlling the pressure in the chamber 15 by adjusting the size of the aperture of the throttle valve in the chamber's discharge system. The size of the hole in the throttle valve is adjusted to control the pressure of the chamber to the desired level with respect to the overall process gas flow to the discharge system, the size of the process chamber, and the pumping setpoint pressure. When the pressure control subroutine 85 is called, the desired target pressure level is received as a variable from the chamber manager subroutine 77a. The pressure control subroutine 85 measures the pressure in the chamber 15 by reading one or more conventional manometers connected to the chamber, compares the measured value with the target pressure, and PIDs from the stored pressure table corresponding to the target pressure. (Proportional, integral, and derivative) values are obtained, and the throttle valve is adjusted according to the PID value obtained from the pressure table. Alternatively, the pressure control subroutine 85 may be written to open or close the throttle valve to a specific open size to adjust the chamber to the desired pressure.
    The heater control subroutine 87 includes program code for controlling the current to the heating device used to heat the substrate 20. Heater control subroutine 87 is also called by chamber manager subroutine 77a and receives a target or setpoint temperature variable. The heater control subroutine 87 measures temperature by measuring the voltage from a thermocouple located on the pedestal 12, compares the measured temperature with the set point temperature, and applies it to the heating device to obtain the set point temperature. Increases or decreases the current drawn. The temperature is obtained from the measured voltage by looking at the corresponding temperature in the stored conversion table or by calculating using a fourth order polynomial. When an embedded loop is used to heat the pedestal 12, the heater control subroutine 87 gradually controls ramp up / down of the current applied to the loop. In addition, a built-in safety mode can be included to detect process safety compliance, which can shut down the heating device if the process chamber 15 is not properly set up.
    The plasma control subroutine 90 includes program code for setting the low frequency and high frequency RF power levels applied to the process electrodes in the chamber and for setting the low frequency RF frequencies used. Similar to the chamber component subroutine described above, the plasma control subroutine 90 is called by the chamber manager subroutine 77a.
    Since the reactor substrate is primarily for illustrative purposes, other plasma CVD devices may also be used, such as, for example, electron cyclotron resonance (ECR) plasma CVD devices, inductively coupled RF high density plasma CVD devices. In addition, various variations of the system described above are possible, such as changes in pedestal design, heater design, RF power frequency, location of RF power connections, and the like. For example, the wafer may be supported by a susceptor and heated by a quartz lamp. The layer and the method of forming the layer in the present invention are not limited to any particular apparatus or specific plasma excitation method.
    III. Deposition of Stable FSG Layer
    In order to form the insulating layer according to the invention, the wafer is mounted to the chamber 15 via a vacuum lock door and placed on the pedestal 12 (FIG. 2A, step 200). The pedestal is then moved to the processing position 14 (step 205). At the processing position 14, the wafer is positioned about 300-600 mils away from the gas distribution branch 11.
    Once the wafer is properly positioned, the wafer and pedestal are heated to about 200-450 ° C. and process gas is introduced from the gas distribution branch into the processing chamber (steps 210 and 215). The process gas comprises a N 2 to SiF 4 as the source of the gas state of the fluorine, the SiH 4 as the source of the gas state in the silicon, the N 2 O as the source of the gas state of oxygen, and as a source of the gas state in the nitrogen Mixture.
    SiH 4 is introduced into the processing chamber at a low flow rate of about 10-30 sccm, and a high flow rate of about 450-500 sccm. SiF 4 is introduced into the processing chamber at a low flow rate of about 5-15 sccm, and a high flow rate of about 800-1000 sccm. N 2 O is introduced into the processing chamber at a low flow rate of about 10-30 sccm, and a high flow rate of about 3800-4000 sccm. N 2 is introduced into the processing chamber at a low flow rate of about 100-300 sccm, and a high flow rate of about 2700-3000 sccm. In addition, helium (He) can also be used as the carrier gas. If used, He is introduced into the processing chamber at a low flow rate of about 10-30 sccm and a high flow rate of about 2700-3000 sccm. Of course, the gases may be introduced into the chamber at a flow rate between the high and low flow rates described above.
    A preferred ratio of N 2 to SiF 4 is between about 4-5: 1, with a value of about 4.4: 1 being preferred. A preferred ratio of N 2 to SiH 4 is between about 3.2-4.5: 1, with a value of about 3.8: 1 being preferred. In addition, the preferred ratio of N 2 to N 2 O is between about 1: 1 and a value of about 1: 2 is preferred.
    The chamber is maintained at a pressure of about 1-6 torr (step 220) and the process gas is excited to a plasma state using a single RF power supply (13.56 MHz) of about 100-2000 W (step 225). The deposition rate of the process is at least about 1.5 μm / min. As a result of the high deposition rate process, a stable insulating film having a reduced dielectric constant is produced.
    As an alternative to step 215 where all components of the process gas are introduced at the same time, the preferred embodiment adopts a strict order in which the components are introduced. In this embodiment, SiF 4 is not introduced in step 215, but instead is introduced when the wafer is heated to the desired process temperature, which corresponds to step 225 where the RF power is turned on and applied to the plasma. This process sequence minimizes the reaction between SiF 4 and SiH 4 that may occur before the plasma is generated, thus preventing HF from forming before the plasma is generated. Although formation of HF during deposition (i.e. after plasma is generated) helps to reduce the amount of unbonded or loosely bound fluorine in the film, HF formed before the plasma is generated is polarized when the plasma is generated. Can be. When polarized, HF forms residues on the membrane that affect the stability and adhesion properties of the membrane. Thus, the process sequence further improves the quality and stability of the membrane by eliminating the formation of HF residues on the membrane.
    Referring to Figure 2B, in a preferred embodiment of the method of the present invention, the deposition process comprises four steps. As shown, the first process step is the stabilization step 250, which includes steps 210-220 of FIG. 2A. The stabilization step 250 is followed by a deposition step 260, which includes step 225 of FIG. 2A and deposition of the film. In a conventional method, a deposition step 260 is followed by a pumping-off step where RF power is turned off, gas flow to the chamber is interrupted, and gas in the chamber is discharged out of the chamber. However, according to a preferred embodiment of the method of the present invention, the terminating step 270 flows into the processing chamber of SiF 4 2-3 seconds prior to blocking other gas flow to the processing chamber in the pumping off step 280. Stop. Testing has shown that some FSG films deposited in this way have no leakage of fluorine, HF, or H 2 O even when heated to at least 700 ° C.
    Blocking the flow of SiF 4 into the chamber before blocking other gas flows reduces the formation of loosely bonded fluorine at the surface of the film, further improving the stability of the deposited FSG film. If there is no significant leakage of fluorine, HF, or H 2 O up to at least 450 ° C. or 700 ° C. according to the deposition method described above, the deposited FSG film and other halogen doped silicon oxide films according to the present invention are at least 7 SiF up to atomic percent (measured using a Fourier Transform Infrared (FTIR) spectrometer with the highest ratio of SiF bond to SiF + SiO bond) and containing at least 16 atomic percent fluorine as measured using SIMS You may. The dielectric constant of the film is about 3.3-3.5 and the deposition rate of the process is typically 1.5-1.8 μm / min, as measured by CV curves at 1 MHz in metal insulator semiconductor (MIS) structures.
    2C shows the effects on the doping efficiency, doping ratio, and film quality of various variables of the process. It can be seen that as the pressure increases, the doping efficiency and film quality improve, but the deposition rate decreases. As the distance between the substrate and the gas distribution center increases, the doping efficiency increases and the deposition rate and film quality decrease. Increasing high RF power corresponds to improved doping efficiency, deposition rate, and film quality. In contrast, the increase in low RF power has no effect on the film. This is because low RF power does not affect the collapse of the SiF 4 bond. Thus, the present invention uses only high RF power.
    2C also shows that the increase in temperature corresponds to the improvement in doping efficiency, deposition rate, and film quality. In addition, as the flow of SiF 4 increases, the doping efficiency increases because more fluorine is introduced. The deposition rate is unaffected (showing that SiF 4 is suitable for high deposition rate processes because the increased fluorine content no longer etches the film), and the quality of the film degrades (stability decreases with decreasing fluorine content). . As shown, an increase in SiH 4 or N 2 O corresponds to an increase in deposition rate. On the other hand, doping efficiency and film quality are poor. Therefore, the addition of N 2 to the process is desirable because the quality of the film improves with increasing N 2 . The deposition rate is not affected by the increase in N 2 flow (since N 2 is an inert gas), but the doping efficiency decreases with the increase in N 2 flow.
    Although N 2 is preferred as the source of nitrogen, other nitrogen sources such as ammonia (NH 3 ) can also be used as process gases for reacting with unbonded or loosely bonded fluorine. Since hydrogen in NH 3 also reacts with fluorine to form HF, it is recognized that NH 3 is a more efficient nitrogen source than N 2 . Since HF is also a volatile gas, it can be released from the chamber along with NF 2 and NF 3 during deposition and after the deposition is completed. It is recognized that N 2 O is a less desirable nitrogen source because relatively large amounts of energy are required to break the NO bond. Less energy is required to break the N 2 bond in the reaction with fluorine to form NF 2 or NF 3 .
    In the most preferred embodiment, a very stable FSG membrane is deposited according to the following preferred conditions: chamber pressure is maintained at 3.7 torr, the distance between the pedestal and the gas distribution center is 400 mils, and the SiH 4 chamber at a rate of 260 sccm. Is introduced into the chamber, N 2 O is introduced into the chamber at a rate of 3000 sccm, N 2 is introduced into the chamber at a rate of 1000 sccm, and He is introduced into the chamber at a rate of 1000 sccm. The process gas is then excited to the plasma state using a high RF power of 1500 W and SiF 4 is introduced into the chamber at a rate of 225 sccm.
    The physical properties, low dielectric constant, high deposition rate and high stability of the FSG film and other halogen-doped silicon oxide films of the present invention make them spin-on in the top layer or IMD layer for HDP CVD. as the insulating layer in -glass, SOG) low k gap-fill layer (low k gap fill layer), and damascene (damascene) process, so it is particularly useful. Referring now to FIG. 3A, an insulating layer 300 deposited as the top layer in accordance with the present invention is shown. The insulating layer 300 appears to be deposited on the high density plasma (HDP) layer 32. As discussed, insulating layer 300 is stable, has good adhesion and low dielectric constant, and is deposited with high deposition rate. Thus, the insulating layer is suitably used as the IMD top layer in processes requiring high throughput, and then a metal layer comprising a titanium layer, which is deposited, is deposited over the top layer. Such layers require high stability because otherwise fluorine in the layer can react with the metal layer. The gap filling capability of the insulating layer 300 in this application is not as important as the HDP layer 320 has good gap filling capability.
    In HDP-CVD reactors, inductively coupled coils are used to generate plasma under very low pressure conditions (millitorr range). The plasma generated by such an HDP-CVD reactor has an ion density of about 2 orders (or more) than the ion density of standard, capacitively coupled PECVD plasma. It is recognized that the low chamber pressure applied in the HDP-CVD reactor provides active species with long average free strokes. This, together with the density of the plasma, allows a significant number of plasma components to reach the bottom portion of the deep and spacing gaps and to deposit films with excellent gap filling properties. In addition, an inert gas of argon or similar weight is introduced into the reaction chamber to facilitate sputtering during deposition. It is recognized that the sputtering element of the HDP deposition etches the deposition on the side of the gap filled, and also contributes to the increase in gap filling of the HDP deposited film.
    Similarly, as shown in FIG. 3B, insulating layer 300 may also be deposited as the top layer over the SOG low k film. As shown, the SOG low k film is deposited according to the following steps: A liquid low k glass film is poured over the metal lines to fill the narrow gap between the metal lines and rotated to make the liquid film coplanar. do. The film is then baked to cure, and the portion above the metal line of the SOG low k layer 330 is etched after the film has cured. The insulating layer 300 is deposited as the top layer on the metal line after the layer 330 is etched. Therefore, the gap filling capability of the insulating layer 300 is not important. It is preferable to use an IMD layer over SOG low k layer 330 because the insulating layer 300 is more stable. The SOG low k layer 330, which is liquid in its natural state, contains more moisture than the insulating layer 300, although baked to cure.
    In other embodiments, the FSG layer of the present invention may be used as the insulating layer 300 in a damascene process. Referring to FIG. 3C, in the damascene process, if insulating layer 300 is first deposited and then etched, metal layer 340 is deposited over the etched and unetched portions of insulating layer 300. Next, the metal layer 340 is etched to form the metal line 340. As shown in FIG. 3D, insulating layer 300 may be deposited as top layer on metal line 340. Alternatively, the insulating layer may be later etched to become an intermediate insulating layer so that another metal layer is deposited.
    4A-4L are test results showing the effect of increasing fluorine concentration in the insulation layer on the stability of the hopper. The fluorine content of the membrane can be monitored using the refractive index (RI) of the membrane. The higher the RI of the membrane, the lower the fluorine content of the membrane. 4A shows Fourier Transform Infrared (FTIR) spectra for different FSG layers deposited under different SiF 4 flows. And Figure 4B is a city, the SiF 4 flow the FSG film RI as a function of the SiF 4 flow correlated with the highest proportion FTIR.
    As shown in Figure 4B, the RI of the FSG membrane decreases with increasing fluorine flow, which translates to an increase in the fluorine content of the membrane. As can be seen in FIGS. 4A and 4B, the SiOF peak, which represents the fluorine content of the membrane, increased as the SiF 4 flow increased from 100 sccm to 400 sccm. Undesired or loosely bound fluorine, which is undesirable, can be detected by the presence of SiF 2 peaks in the spectrum. 4A-4B show by FTIR peak ratio that the maximum amount of fluorine that can be doped into a film without the presence of SiF 2 under the conditions described above is 7 atomic percent, which is an RI value of 1.406 and a SiF 4 flow of about 230 sccm. Corresponds to.
    The influence of power, chamber pressure, and SiF 4 on the fluorine doping of the FSG film was studied based on a 1 μm thick sample film prepared under the following conditions: The chamber pressure was maintained at about 3.7 torr, and pedestal and gas distribution. The distance between the centers is about 400 mils, SiH 4 is introduced into the chamber at a rate of about 260 sccm, N 2 O is introduced into the chamber at a rate of about 3000 sccm, and N 2 is introduced into the chamber at a rate of about 1000 sccm. At a high RF power of about 1500 W, the process gas is excited to a plasma state. The rate at which SiF 4 is introduced into the chamber varies from 100 to 3000 sccm, the power varies from 700 to 1500 W, and the chamber pressure varies from 3.5 to 5 torr.
    4C shows the fluorine content of the membrane as a function of power and SiF 4 flow. As illustrated, in accordance with the SiF 4 flow and the power increases film RI is decreased, and thus in accordance with the SiF 4 flow and power are increased fluorine content of the film was increased.
    4D shows the fluorine content of the membrane as a function of pressure and SiF 4 flow. As shown, the RI of the film decreased with increasing SiF 4 flow and pressure, but unlike power, this relationship is not straight. At about 250 sccm of SiF 4 flow, the fluorine content is saturated and remains substantially constant regardless of the fluorine flow.
    4E shows RI and stress of 1 μm membrane when placed in clean room over 14 days. This shows that the membrane is stable because the RI and stress of the membrane remain relatively constant.
    4F shows the FTIR spectrum of the membrane after boiling in water for 30 minutes. Since the FTIR spectrum after the water test shows no formation of any H-O-H bonds, the spectrum shows that the membrane is stable.
    Figure 4G is and contrast the addition after the boiling water test the film, the deposited film when the N 2 and N 2 to be deposited without the membrane stability. As shown, the film deposited without N 2 is unstable as its FTIR spectrum shows that HOH bonds are formed around about 3350 cm −1. Thus, FIG. 4G confirms that the use of N 2 further improves the stability of the membrane.
    4H shows the FTIR of the membrane before and after the membrane undergoes annealing at 450 ° C. for 30 minutes. Annealing tests were conducted to determine the compatibility of the integration process. As shown in FIG. 4H, the Si—O—F peaks did not change. In other words, the fluorine content of the membrane was not reduced. Thus, the membrane is stable.
    In addition, a thermal desorption spectra (TDS) was performed to determine at what temperature the fluorine in the membrane began to leak. 4I shows the TDS of the deposited film without terminating step 270. As shown, fluorine started leaking at 475 ° C while HF started leaking at 500 ° C. As shown in FIG. 4J showing the TDS of the deposited film with termination step 270, fluorine and HF did not begin leaking until about 700 ° C. TDS obtained after 14 days shows the same result, indicating that the deposited FSG membrane is stable.
    Membranes deposited according to the invention also have good adhesion properties. As mentioned, the termination step 270 reduces fluorine that is loosely bound to the surface of the membrane. Thus, the film adheres well to various metals and dielectric layers, examples of which include aluminum, titanium, titanium nitride, tungsten, and dielectric antireflective coatings. 4K illustrates this through photographs of aluminum patterns taken immediately after deposition, after boiling for 30 minutes in water, and after 3 days. As can be seen, the film boiled in water for 30 minutes, but after 3 days, it showed no corrosion, cracking or peeling, and thus had excellent adhesive properties.
    Finally, the RI value of the film, the SiOF / SiO peak ratio, and the uniformity of the amount of fluorine doped in the film were measured to determine the amount of fluorine throughout the film. As shown in FIG. 4L, the fluorine content throughout the membrane was constant at 16 atomic percent. Thus, this test shows that the fluorine content of the membrane is constant throughout the membrane. This in turn indicates that the dielectric constant of the membrane is constant throughout the membrane.
    All numerical values for the various gas introduction ratios discussed above are based on resistance heated DxZ chambers prepared for 200 mm wafers manufactured by Applied Materials. Chambers of different sizes or made by different manufacturers may exhibit different gas introduction rates.
    Thus, the method of the present invention is not limited by the specific variables given above. Those skilled in the art will appreciate that other processing conditions and different reactant sources may be used without departing from the spirit of the present invention. Other equivalents or alternative methods of depositing an insulating layer in accordance with the present invention will be apparent to those skilled in the art. These equivalents and alternatives are included within the scope of the present invention.
    By way of example only, the invention specifically illustrates a process using SiF 2 as the source of silicon and N 2 O as the source of oxygen, but using other silicon sources such as TEOS or other oxygen sources such as O 2 , CO, etc. It is also possible. Therefore, the scope of the invention should not be determined with reference to the above description, but instead should be determined with reference to the appended claims, along with the full scope of equivalents thereof.
    The present invention has the effect of providing a halogen doped layer with low dielectric constant and improved stability even at high halogen doping levels.
    权利要求:
    Claims (20)
    [1" claim-type="Currently amended] A process for depositing a halogen doped silicon oxide layer over a substrate in a substrate processing chamber, the process comprising:
    Introducing a process gas comprising a silicon source, an oxygen source, a halogen source, and a nitrogen source into the chamber; And
    Depositing a plasma from the process gas to deposit the halogen-doped silicon oxide layer on the substrate.
    [2" claim-type="Currently amended] The method of claim 1,
    Wherein said halogen source comprises a fluorine source.
    [3" claim-type="Currently amended] The method of claim 2,
    And the silicon oxide layer can contain up to at least 16 atomic percent fluorine.
    [4" claim-type="Currently amended] The method of claim 2,
    Wherein the silicon oxide layer is deposited on the substrate at a deposition rate of at least about 1.5 μm / min.
    [5" claim-type="Currently amended] The method of claim 2,
    Wherein the silicon oxide layer has an overall dielectric constant of about 3.3-3.5.
    [6" claim-type="Currently amended] The method of claim 2,
    Wherein the silicon oxide layer can be heated to at least 475 ° C. before fluorine leakage occurs.
    [7" claim-type="Currently amended] The method of claim 2,
    The introduction of the fluorine source into the chamber is stopped 2-3 seconds before the end of another gas flow into the chamber, so that the silicon oxide layer can be heated to at least 700 ° C. before leakage occurs. Jit process.
    [8" claim-type="Currently amended] The method of claim 2,
    Maintaining a pressure of about 1-6 torr in the processing chamber;
    Heating the substrate to a temperature of about 200-450 ° C .; And
    Depositing plasma at a high frequency RF power of about 100-2000 W at a frequency of about 13.56 MHz.
    [9" claim-type="Currently amended] The method of claim 2,
    The fluorine source comprises SiF 4 gas and is introduced into the processing chamber at a rate of about 5-1000 sccm.
    [10" claim-type="Currently amended] The method of claim 9,
    To further improve the quality and stability of the silicon oxide layer, the SiF 4 gas is introduced into the processing chamber when the substrate has reached the desired process temperature.
    [11" claim-type="Currently amended] The method of claim 2,
    Wherein the silicon source comprises SiH 4 and is introduced into the semiconductor processing chamber at a rate of about 10-500 sccm.
    [12" claim-type="Currently amended] The method of claim 11,
    Wherein said oxygen source comprises N 2 O and is introduced into said processing chamber at a rate of about 10-4000 sccm.
    [13" claim-type="Currently amended] The method of claim 12,
    Wherein the nitrogen source comprises N 2 gas and is introduced into the processing chamber at a rate of about 10-3000 sccm.
    [14" claim-type="Currently amended] A process for depositing a high deposition rate FSG layer having a low dielectric constant on a substrate in a semiconductor processing chamber, the process comprising:
    Heating the substrate to a temperature of about 200-450 ° C .;
    Introducing a process gas comprising SiF 4 , an oxygen source, SiH 4 , and N 2 into the chamber;
    Maintaining the chamber at a pressure of about 1-6 torr; And
    Forming a plasma from the process gas to deposit the FSG layer on the substrate.
    [15" claim-type="Currently amended] The method of claim 14,
    Depositing an HDP gap fill layer; And
    Depositing the FSG layer as a top layer on the HDP layer.
    [16" claim-type="Currently amended] The method of claim 14,
    Depositing a SOG low k film; And
    Depositing the FSG layer as an uppermost layer on the SOG low k film.
    [17" claim-type="Currently amended] The method of claim 14,
    And the FSG film is compatible to be used as an insulating film in a damascene process.
    [18" claim-type="Currently amended] An integrated circuit formed by the process of claim 14.
    [19" claim-type="Currently amended] A process for depositing a high deposition rate FSG layer having a low dielectric constant on a substrate in a semiconductor processing chamber, the process comprising
    Heating the substrate to about 200-450 ° C .;
    Introducing a process gas comprising SiH 4 , an oxygen source, and N 2 into the chamber;
    Maintaining the chamber at a pressure of about 1-6 torr;
    Introducing the SiF 4 gas into the chamber as a high RF power is turned on to form a plasma from the process gas and SiF 4 gas to form the FSG layer on the substrate; And
    Terminating the introduction of SiF 4 gas into the chamber at least 2-3 seconds before the introduction of the process gas into the chamber is terminated.
    [20" claim-type="Currently amended] A substrate processing apparatus,
    Processing chamber;
    A gas delivery system configured to deliver a process gas to the processing chamber;
    A plasma generating device configured to form a plasma from the process gas;
    A controller configured to control the gas delivery system and the plasma generation system; And
    A memory coupled with the controller, the computer including a computer readable medium having a computer readable program therein for directing operation of the substrate processing apparatus,
    The computer readable program includes:
    A first set of computer instructions for controlling the gas delivery system for introducing a process gas comprising a halogen source, a silicon source, a nitrogen source, and an oxygen source into the substrate processing chamber; And
    And a second set of computer instructions for controlling the plasma generation system for forming a plasma from the process gas and depositing a silicon oxide layer on a substrate in the chamber.
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    同族专利:
    公开号 | 公开日
    DE69837124D1|2007-04-05|
    JP4323583B2|2009-09-02|
    US6077764A|2000-06-20|
    EP0874391A2|1998-10-28|
    JPH118235A|1999-01-12|
    US6395092B1|2002-05-28|
    EP0874391B1|2007-02-21|
    EP0874391A3|1998-12-30|
    DE69837124T2|2009-08-20|
    KR100550419B1|2006-04-21|
    TW380286B|2000-01-21|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-04-21|Priority to US8/837,641
    1997-04-21|Priority to US08/837,641
    1997-04-21|Priority to US08/837,641
    1998-04-21|Application filed by 조셉제이.스위니, 어플라이드머티어리얼스,인코포레이티드
    1998-11-25|Publication of KR19980081561A
    2006-04-21|Application granted
    2006-04-21|Publication of KR100550419B1
    优先权:
    申请号 | 申请日 | 专利标题
    US8/837,641|1997-04-21|
    US08/837,641|1997-04-21|
    US08/837,641|US6077764A|1997-04-21|1997-04-21|Process for depositing high deposition rate halogen-doped silicon oxide layer|
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